1. Field of the Invention
The present invention generally relates to complementary MIS transistors having P- and N-channels on a common substrate, and more particularly to a complementary MIS transistor including a well formed in a substrate, with source and drain regions formed in the well, wherein the distribution profile of impurities is optimized in the well and further in the source and drain regions for facilitating miniaturization of the device.
2. Description of the Related Arts
With recent progress in the fabrication process of miniaturized semiconductor devices, there is a tendency that the operation of miniaturized N-channel transistors tends to be affected by the hot carrier effect. Similarly, there is a tendency that modern P-channel transistors exhibit appreciable short channel effect. In any of these cases, the device suffers from the problem of variation of the threshold voltage, and such a variation of the threshold voltage has become a limiting factor for further miniaturization of the device.
In order to suppress the hot carrier effect in the N-channel MIS transistors, a so-called LDD (Lightly-Doped Drain) structure has been proposed. In the LDD structure, an N-type region of reduced impurity concentration level is formed adjacent to the usual N-type drain region for relaxing the large electric field formed adjacent to the drain region. When forming the drain region with such an LDD structure, on the other hand, it has been necessary to provide a mask to extend over a length larger than the gate length of the gate electrode. More specifically, there has been a need to form an oxide film to cover the side wall of the gate electrode as a mask by a deposition process such as CVD. Thus, the foregoing LDD structure has a drawback in that the fabrication process thereof inevitably becomes complex.
Meanwhile, the U.S. Pat. No. 4,924,277 describes a structure of a complementary MIS transistor that has an N-type diffusion region formed to surround the source region and the drain region in both the N-channel MIS transistor and the P-channel MIS transistor that form the complementary MIS transistor, such that the N-type diffusion region suppresses the hot carrier effect in the N-channel transistor by relaxing the electric field. In the P-channel transistor, on the other hand, the N-type diffusion region suppresses the short channel effect and reduces the punch-through effect.
FIG. 11 shows the structure proposed by the foregoing reference.
Referring to the drawing, the device includes a P-type silicon substrate 50 in which a P-type well 51a and an N-type well 51b are formed, wherein a P-channel transistor is formed on the N-type well 51b, while an N-channel transistor is formed on the P-type well 51a. Each transistor is isolated from the other transistor electrically by an isolation oxide film 56 that is formed by the usual LOCOS process. Further, the wells 51a and 51b carry thereon corresponding gate insulation films 57a and 57b, and the gate insulation films 57a and 57b in turn carry thereon corresponding gate electrodes 58a and 58b.
At both lateral sides of the gate electrode 58a, N-type diffusion regions 61a and 62a are formed according to a self-alignment process that uses the gate electrode 58a as a self-alignment mask. Similarly, N-type diffusion regions 61b and 62b are formed at both lateral sides of the gate electrode 58b while using the gate electrode 58b as a self-alignment mask. Further, an N-type diffusion region 63a of increased impurity concentration level is formed within the foregoing N-type diffusion region 61a as the source region of the N-channel transistor. Similarly, another N-type diffusion region 64a of increased impurity concentration level is formed within the N-type diffusion region 62a as the drain region of the same N-channel transistor. In the N-type diffusion region 61b, on the other hand, a P-type diffusion region 63b is formed as the source of the P-channel transistor with a large impurity concentration level, while in the N-type diffusion region 62b, another P-type diffusion region 64b of increased impurity concentration level is formed as the drain of the same P-channel transistor.
Referring to FIG. 11, it will be noted that each of the N-type diffusion regions 61a, 62a, 61b and 62b is formed to have an increased lateral size as well as increased vertical depth as compared with the corresponding diffusion region that is accommodated therein. Thus, the diffusion region 61a has a lateral size and a vertical depth larger than those of the diffusion region 63a, the diffusion region 62a has a lateral size and a vertical depth larger than those of the diffusion region 64a, the diffusion region 61b has a lateral size and a vertical depth larger than those of the diffusion region 63b, and the diffusion region 62b has a lateral size and a vertical depth larger than those of the diffusion region 64b. The foregoing N-type diffusion regions 61a, 62a, 61b and 62b are doped to have respective impurity concentration levels that are set higher than the impurity concentration level of the corresponding P-type well 51a or corresponding N-type well 51 b. Further, the impurity concentration levels of the foregoing diffusion regions 61a, 62a, 61b and 62b are set substantially smaller than the impurity concentration level of the corresponding N-type or P-type diffusion regions formed therein with increased impurity concentration level. Thus, the impurity concentration level of the diffusion region 61a is smaller than the impurity concentration level of the corresponding diffusion region 63a, the impurity concentration level of the diffusion region 62a is smaller than the impurity concentration level of the corresponding diffusion region 64a, the impurity concentration level of the diffusion region 61b is smaller than the impurity concentration level of the corresponding diffusion region 63b, and the impurity concentration level of the diffusion region 62b is smaller than the impurity concentration level of the corresponding diffusion region 64b.
Further, a protection film 59, typically of a borophosphate glass, is provided so as to cover the oxide isolation film 56 as well as the gate oxide films 57a, 57b, and the gate electrodes 58a 58b. The protection film 59 is provided with contact holes 70 for exposing the diffusion regions 63a and 64a as well as the diffusion regions 63b and 64b. In correspondence to the contact holes 70, ohmic electrodes 71 are provided. In the complementary MIS transistor having the foregoing structure, the N-type diffusion region 62a, provided in the region of the N-channel transistor, causes a decrease in large electric field formed in the channel region in correspondence to the pinch-off point that in turn is formed adjacent to the drain region. Thereby, the degradation of the device characteristics, caused for example by the avalanche injection of hot carriers into the gate oxide film 57a, is avoided successfully. In the P-channel transistor, the N-type diffusion region 62b functions as a punch-through stopper and suppresses the unwanted degradation of the device characteristics such as the decrease of threshold voltage. In the conventional P-channel MIS transistors that use polysilicon doped with phosphorus with a large concentration level for the gate electrode 58b, there has been a tendency that a metallurgical P-N junction, formed in the channel region immediately under the gate electrode as a buried channel structure, tends to cause punch-through of the carriers. Thus, conventional P-channel MIS transistors have been vulnerable to the short channel effect as compared with N-channel MIS transistors. As mentioned previously, the complementary MIS transistor of the foregoing prior art reference successfully suppresses the short channel effect pertinent to the conventional device by providing the N-type diffusion region 62b that acts as the punch-through stopper.
In the N-channel MIS transistor, it is essential to provide the N-type diffusion region 62a, which reduces electric field, to have a sufficiently large lateral size in order to achieve the desired suppression of hot carrier degradation. However, formation of the diffusion region to have such a large lateral size requires a long annealing time for the diffusion process, and such a prolonged diffusion process inevitably results in an increased depth of the diffusion region. Thereby, it will be understood that the controlled formation of the drain region becomes increasingly difficult with decreasing device size. Ultimately, one encounters the problem of short channel effect again, and the fabrication of the device with controlled threshold voltage becomes extremely difficult.
In the P-channel MIS transistor wherein the N-type diffusion regions 61b and 62b are formed within the N-type well 51b with an increased impurity concentration level as compared with the well 51b, the depth of the diffusion regions 61b and 62b becomes inevitably larger than the depth of the P-type diffusion regions 63b and 64b similarly to the N-channel transistor, as long as the diffusion regions 61b and 62b are formed to have an increased lateral size as compared with the diffusion regions 63b and 64b. Thereby, the depletion regions formed between the source region 63b and the N-type well 51b and between the drain region 64b and the N-type well 51b, inevitably have a width that is smaller than usual width of the depletion region formed in the P-channel MIS transistors. Such a reduction in the width of the depletion region in turn invites increase of junction capacitance and the operational speed of the device is deteriorated as a result.